1. Field of the Invention
The present invention relates to a current comparator with hysteresis, and more particularly, to a current comparator capable of determining transition points in a hysteresis curve.
2. Description of the Prior Art
Please refer to FIG. 1, which shows circuitry of a hysteresis current comparator 10 according to the prior art. The current comparator 10 includes five NMOS transistors M1, M2, M5, M6 and M8, and three PMOS transistors M3, M4 and M7.
Transistors M1 and M2 are driven by the voltage of a node N1 through the gates. Transistors M5 and M6 of the hysteresis current comparator 10 are regarded as a current sink, driven by the voltage of a node N2 through the gates. The drains of transistors M1 and M3 are connected to a node N3. In addition, the node N3 connected to the drains of transistors M1 and M3 is further connected to the gates of transistors M3 and M4.
Similarly, the drains of transistors M2 and M4 are connected to a node N4, which is further connected to the gates of transistors M7 and M8. Additionally, the two inputs of the current comparator 10, nodes N5 and N6, are respectively connected to the sources of transistors M1 and M2. The output of the current comparator 10 is connected to the node N4. The sources of transistors M3 and M4 are connected to a voltage source Vdd, and so are the drain of transistor M8 and the source of transistor M7. The drain of transistor M7 is connected to the node N5 and the source of transistor M8 is connected to the node N6. In FIG. 1, the input current I1 passes through the node N5 while a reference current I2 passes through the node N6.
Please refer to FIG. 2, which is a graph of current vs. voltage for the circuit in FIG. 1. Transistors M7 and M8 and the reference current I2 control the hysteresis curve of the current comparator 10. Please refer to FIG. 1 again. When the output voltage Vout is at low level, transistor M7 is driven so that the output current IM7 of transistor M7 passes through the node N5. In the same time, the input current I1 also passes through the node N5 and thereby transfers the output voltage Vout of the current comparator 10. At this moment, the output voltage Vout is (−Zv((I1+IM7)−I2)). The output voltage Vout is transferred to high level only when the value of ((I1+IM7)−I2) is negative. Conversely, when the output voltage Vout is high, transistor M8 is driven so that the input current IM8 passes through the node N6 while the reference current I2 passes through the node N6 and thereby changes the output voltage Vout of the current comparator 10. At this moment, the output voltage Vout is (−Zv(I1−(I2+IM8))). The output voltage Vout is transferred to low level only when the value of (I1−(I2+IM8)) is positive.
When transistor N7 is turned on and the value of ((I1+IM7)−I2) is negative, the output voltage Vout will be transferred from low to high level at a transition point a. On the contrary, when transistor M8 is driven and the value of (I1−(I2+IM8)) is positive, the output voltage Vout is transferred from high to low level at a transition point b. Therefore, in FIG. 2, the positions of the transition points a and b are respectively controlled by transistors M7 and M8. However, transistors M7 and M8 are different types of transistors. Transistor M7 is a PMOS transistor while transistor M8 is an NMOS transistor. During manufacture, it is difficult to control the parameters of transistors M7 and M8 to determine the positions of the transition points a and b and thereby the hysteresis curve of the current comparator 10 is not as expected. For example, suppose that the required hysteresis curve is a curve in which the reference current I2 is zero and the transition points a and b are respectively −200 uA and 200 uA. However, due to process variations, the transition points a and b might shift, the transition point a shifting to −230 uA and the transition point b shifting to 210 uA. Therefore, we cannot get the required hysteresis curve mentioned above.